1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a BGA (Ball Grid Array) integrated circuit package having arrayed solder balls as I/O leads.
2. Description of Related Art
An integrated circuit package of the ball-grid-array (BGA) type is one that includes an array of electrically-conductive balls, such as solder balls, on the bottom side of the substrate for external connections of the integrated circuit package. The BGA package allows the integrated circuit package to be able to incorporate an increased number of I/O connections as compared to the conventional QFP (Quad Flat Package) devices. This benefit allows the BGA integrated circuit package to embed high-complexity and high-performance integrated circuits therein.
One problem arising from BGA integrated circuit packages having high-complexity and high-performance semiconductor chips, however, is that electrical noise would easily occur among the electronic components and electric circuits. The primary sources of such electrical noise are, for instance, switching noise which occurs on a current path arising from rapid current switching and crosstalk which occurs in a current path resulting from mutual capacitance and inductance between two adjacent current paths. Meanwhile, mutual inductance and self-inductance of conductive routes used for transmitting electrical signals between the semiconductor die and external electronic devices are also insignificant of electrical noise.
In addition, the electromagnetic radiations from the various electronic components in the integrated circuit package would cause undesired electromagnetic interference (EMI) to the nearby electronic devices, which would adversely affect the integrated circuit operation and electronic performance. Therefore, in the design and manufacture of integrated circuit packages, it is required to reduce the electromagnetic interference to minimum.
Conventionally integrated circuit packages are typically encapsulated in a resin-made encapsulate, and since resins are poor in thermal conductivity, the dissipation of the chip-produced heat during operation would be a problem. One solution is to provide a heat sink in the package. This practice, however, would increase the overall package weight and the complexity of the fabrication process, making the manufacture of the integrated circuit package quite laborious and cost-ineffective.
FIG. 5 is a schematic sectional diagram of a conventional BGA integrated circuit package disclosed in the U.S. Pat. No. 5,640,048, which is designed to solve the above-mentioned problems. As shown, this BGA integrated circuit package, as designated by the reference numeral 50, includes a plurality of upper conductive traces 8A, 8B, 8C, 8Cxe2x80x2 and lower conductive traces 10A, 10B, 10C, 10Cxe2x80x2. The heat produced by the semiconductor chip 12 is conducted through a thermal path composed of the upper conductive traces 8C, the vias 6C, the ground plane 60, the lower conductive traces 10C, and the solder balls 14C to the ground traces 20C on the printed circuit board 18. Since the distance between the ground plane 60 and the semiconductor chip 12 is less than the distance between the printed circuit board 18 and the semiconductor chip 12, it also allows the ground plane 60 to dissipate part of the chip-produced heat during operation, thus allowing an increased heat-dissipation efficiency. In addition, since the ground plane 60 is located at a closer position to the semiconductor chip 12 than the printed circuit board 18, it allows a reduced current return path, which can help reduce the mutual inductance between traces and hence the simultaneous switching noise. Moreover, the ground plane 60 also can help reduce the mutual coupling effect between the signal traces in the integrated circuit package, thus reducing crosstalk.
One drawback to the forgoing patent, however, is that electromagnetic interference is still a problem. Still one drawback is that the substrate of the BGA integrated circuit package is made by adhering a copper layer on the underside of a circuit board 52 having a core layer 56 sandwiched between symmetrically arranged copper layers, or alternatively on the aboveside of a circuit board 54 having a core layer 58 sandwiched between symmetrically arranged copper layers. This structure, however, cannot be manufactured by the currently-employed process for a two-layer BGA substrate, making the manufacture cost considerably high. Moreover, it is required to dimension the substrate to a thickness of up to the range from 0.02 inch to 0.03 inch (0.5 mm to 0.8 mm) for the purpose of providing sufficient rigidity to prevent the substrate from being bent and deformed during the mounting of the substrate on the circuit board. This substrate thickness, however, would make the overall package size unsatisfactorily large.
It is therefore an objective of this invention to provide a BGA integrated circuit package, which has a better heat-dissipation efficiency and an improved electronic performance than the prior art.
It is another objective of this invention to provide a BGA integrated circuit package, which can help reduce electromagnetic interference which would otherwise interfere with external electronic devices.
It is still another objective of this invention to provide a BGA integrated circuit package, which can be manufactured utilizing the existent two-layer BGA substrate so as to make the manufacture more cost-effective than the prior art.
It is yet another objective of this invention to provide a BGA integrated circuit package, which has a reduced package size as compared to the prior art.
In accordance with the foregoing and other objectives, the invention proposes an improved BGA integrated circuit package. The BGA integrated circuit package of the invention comprises: (a) a semiconductor chip; (b) a substrate on which the semiconductor chip is mounted, which is composed of a core layer interposed between first conductive traces and second conductive traces, with the first conductive traces and second conductive traces being electrically connected to each other through a plurality of vias formed in the core layer; (c) a plurality of conductive balls electrically connected to the second conductive traces; (d) a ground metallic layer disposed over the first conductive traces, which defines a chip-receiving cavity for receiving the semiconductor chip therein; (e) a set of bonding wires for electrically coupling the semiconductor chip to the first conductive traces; and (f) an encapsulate which encapsulates the semiconductor chip, the bonding wires, the first conductive traces, and the ground metallic layer.
Since the ground metallic layer is made of a metal such as copper and formed around the semiconductor chip and located near the semiconductor chip and the first conductive traces, it can shorten the current return path, thereby reducing the inductance occurring between current paths and hence the simultaneous switching noise in the integrated circuit package. Moreover, it can help reduce the crosstalk between neighboring signal traces. Still more, since the ground metallic layer can act as a shield to electromagnetic radiation, it can reduce the electromagnetic interference. In addition, a portion of the surface of the ground metallic layer may be exposed to the outside of the encapsulate whereby the ground metallic layer provides the semiconductor chip with a direct heat-dissipation part to the ambient. As a result, the heat-dissipation efficiency of the BGA integrated circuit package of the invention is improved. These benefits make the BGA integrated circuit package of the invention more advantageous to use than the prior art of the U.S. Pat. No. 5,640,048.
The first conductive traces includes first power traces, first signal traces, first ground traces, and first thermal traces; and correspondingly, the second conductive traces include second power traces, second signal traces, second ground traces, and second thermal traces. These paired traces are interconnected respectively by vias formed in the core layer of the substrate. The chip-produced heat during operation can be dissipated through a thermal path connected to the thermal traces on the printed circuit board, which is composed of the first thermal traces, the thermal vias, the second thermal traces, and the thermal solder balls.
Further, the BGA integrated circuit package is formed with a ground path composed of the ground vias, the first ground traces, the second ground traces, the ground solder balls, and the ground metallic plane. This ground path allows a shortened signal return path, thereby reducing the ground bounce.
The BGA integrated circuit package of the invention can be further incorporated with a heat-dissipation device adhered to the ground metallic layer, allowing the heat generated from the semiconductor chip to be conducted via the ground metallic layer to the heat-dissipation device for dissipation to the atmosphere through the exposed surface of the heat-dissipation device which is exposed to the outside of the encapsulate.
The semiconductor chip is accommodated within the chip-receiving cavity, thereby making the integrated circuit package of the invention lower in profile than the prior art. Moreover, as the incorporation of the ground metallic layer enhances the rigidity of the substrate, the core layer of the substrate can be reduced in thickness which allows the overall profile of the integrated circuit package of the invention to be further reduced.
The semiconductor chip can be connected to the first conductive traces through the flip-chip bonding.
In another embodiment, the ground metallic layer can be formed by interposing a core layer between two conductive metal sheets. Further, this two-layer structure can be firmly adhered to first conductive traces of the substrate through the use of a pre-preg adhesive. Since the use of the two-layer structure as the ground metallic layer provides the integrated circuit package of the invention with an increased rigidity as compared to the one used in the previous embodiments, it allows the mounting of the ground metallic layer to the substrate to be easily and conveniently carried out. As a result, the integrated circuit package of the invention can be easier and more cost-effective to manufacture than the previous embodiments.